The present invention relates to a signal processor incorporating digital to analog converters. More particularly, the present invention relates to methods and apparatus for varying the circuit configuration, output voltage range (the difference between the lowest possible output voltage and the highest output voltage) and level (the variance, however small or large, between ground and the lower limit of the output signal range) of such a signal processor.
A digital to analog converter (DAC) converts a digital input word to an analog output. Signal processors which utilize DACs typically operate in either a unipolar or bipolar mode, both of which will be briefly described below.
The generic equation for determining VOUT in unipolar and bipolar signal processor is shown in Equation 1:                               V          OUT                =                  G          *                      V            REF                    *                      (                                          K1                *                                                      INPUT                    ⁢                                          xe2x80x83                                        ⁢                    CODE                                                        MAX                    ⁢                                          xe2x80x83                                        ⁢                    INPUT                    ⁢                                          xe2x80x83                                        ⁢                    CODE                                                              -              K2                        )                                              (        1        )            
where MAX INPUT CODE is the maximum value of INPUT CODE or 2nxe2x88x921, when INPUT CODE is an n-bit digital word, G is the gain of the signal processor and K1 and K2 are constants that determine the configuration mode. In the unipolar mode configuration (e.g., when the output voltage varies from 0 volts to 5 volts or from 2.5 volts to 7.5 volts) K1=1 and K2=0 so that VOUT varies between 0 and |G*VREF|. In the bipolar mode configuration (e.g., output voltage varies from xe2x88x925 volts to 5 volts, K1=2 and K2=1 so that VOUT varies between xc2x1G*VREF.
FIG. 1 shows an example of a previously known unipolar signal processor 10, which receives an input voltage VREF, control signal UPDATE and INPUT CODE, and generates analog output VOUT. INPUT CODE typically is an n-bit digital word that signal processor 10 uses to convert digital input voltage VREF to analog output VOUT. UPDATE is a binary input signal which determines when the INPUT CODE can be used to convert VREF to produce a new VOUT. When UPDATE is LOW, VOUT remains substantially constant. When UPDATE changes from LOW to HIGH, DAC 10 converts VREF to analog output VOuT based on the INPUT CODE.
Signal processor 10 includes current converter (DAC) stage 12, op-amp 22, capacitor 24 feedback resistor 20 and switch-resistance compensation element SF. Current converter stage 12 includes R-2R ladder 14, switches 161 to 16n and latch and decoder 18 and switch-resistance compensation element ST.
The R-2R ladder 14 is coupled between VREF and switches 161 to 16n, and includes n branches each containing a resistor 25i and a termination branch having resistor 27 and switch-resistance compensation element ST. The R-2R ladder 14 includes a resistor 23 between the top nodes of each branch. Typically, resistors 25 are twice as large as resistors 23. Termination branch resistor 27 is of the same value as resistors 25i. Switch-resistance compensation element ST of the termination branch is connected to GROUND. Resistor 27 and switch-resistance compensation element ST of the termination branch serve to balance the impedance of the R-2R ladder 14 at each top node. Without the termination branch, the current flowing through each branch would differ and thereby cause errors in the current conversion process.
The INPUT CODE in combination with the reference voltage causes an intermediate current, IDAC to flow according to Equation 2, R is the input impedance of the R-2R ladder:                               I          DAC                =                              (                                          V                REF                            R                        )                    *                      (                                          INPUT                ⁢                                  xe2x80x83                                ⁢                CODE                                            MAX                ⁢                                  xe2x80x83                                ⁢                INPUT                ⁢                                  xe2x80x83                                ⁢                CODE                                      )                                              (        2        )            
Feedback resistor 20, feedback switch-resistance compensation element SF, op-amp 22 and capacitor 24 form a current to voltage converter. The op-amp 22 has an inverting input (xe2x88x92) coupled to current converter 12, feedback resistor 20 and capacitor 24, a non-inverting input (+) coupled to GROUND, and an output coupled to VOUT. Capacitor 24 is coupled between inverting input (xe2x88x92) and VOUT to provide a first feedback loop around the op-amp 22. This first feedback loop is not required for operation. Feedback resistor 20 and switch-resistance element SF are coupled between inverting input (xe2x88x92) and VOUT to provide a second feedback loop around the op-amp 22. Switch-resistance compensation element SF, like switch-resistance compensation element ST, is required for matching of the on-resistance of switches 16i from the R-2R ladder 14.
The current to voltage converter operates to convert intermediate current IDAC to the output voltage VOUT. The resulting, VOUT is shown in Equation 3:                               V          OUT                =                                            -                              I                DAC                                      *            R                    =                                    -                              V                REF                                      *                          (                                                INPUT                  ⁢                                      xe2x80x83                                    ⁢                  CODE                                                  MAX                  ⁢                                      xe2x80x83                                    ⁢                  INPUT                  ⁢                                      xe2x80x83                                    ⁢                  CODE                                            )                                                          (        3        )            
FIG. 2 shows a bipolar signal processor 30 which includes circuit 14, comprising an inverting amplifier 40 and gain resistors 42 and 44 coupled between VREF, and current converter 12. Amplifier 40 and gain resistors 42 and 44 serve to invert input voltage VREF. Inverted VREF (i.e., xe2x88x92VREF) is used to generate IREF, as described above in FIG. 1. Alternatively, amplifier 40 and resistors 42 and 44 could be located external to signal processor 30 in the signal path.
VREF is also coupled to level resistor 38, which is then coupled to the inverting input of op-amp 22 via switch-resistance compensation element SO. Capacitor 24 and feedback resistor 36 are coupled between inverting input (xe2x88x92) and VOUT to provide first and second feedback loops, respectively, around op-amp 22. This is one technique for applying opposite polarity to the current converter and to the level circuitry, a condition which is required for operation of the DAC. However, other suitable techniques for establishing this condition are well-known in the art. Switch-resistance compensation elements SO and SF are included in the circuit to match the impedance of the resistors and switches in the R-2R ladder 14 described above in FIG. 1.
A first signal path from VREF to VOUT via level resistor 38, feedback resistor 36 and op-amp 22, inverts the input signal VREF at VOUT. A second signal path from VREF to VOUT via gain resistors 42, 44, inverting amplifier 40, current converter 12 and op-amp 22, produces the voltage shown in Equation 4 at VOUT:
V=xe2x88x92IDAC*2Rxe2x80x83xe2x80x83(4)
where IDAC is defined by Equation 2. The total output voltage at VOUT is the combination of the voltage from the first and second signal paths and is shown in Equation 5:                               V          OUT                =                              V            REF                    *                      {                                          2                *                                  {                                                            INPUT                      ⁢                                              xe2x80x83                                            ⁢                      CODE                                                              MAX                      ⁢                                              xe2x80x83                                            ⁢                      INPUT                      ⁢                                              xe2x80x83                                            ⁢                      CODE                                                        }                                            -              1                        }                                              (        5        )            
Equation 5 equals the desired result of the voltage conversion shown in Equation 1 for a bipolar configuration where K1=2, K2=1 and G=1. Thus, for a 10 volt input (VREF=10), the first signal path yields a voltage of xe2x88x9210 volts, while the second signal path provides a voltage between 0 and 20 volts based on the INPUT CODE so that VOUT has a range of xc2x110 volts.
The prior art consists of various configurations of signal processor 10 and/or signal processor 30 from FIGS. 1 and 2 in monolithic or discrete form. The configuration was typically chosen to be unipolar or bipolar only and connected permanently as such. To make the configuration switchable between unipolar and bipolar modes, however, extra discrete switches and operational amplifiers have been added, as shown in FIG. 3.
In FIG. 3, non-inverting amplifier 52 and switch 56 are connected to the signal processor 30 from FIG. 2. Amplifier 52 has inverting input (xe2x88x92) and its output coupled to resistor 38 and noninverting input (+) coupled to switch 56. Switch 56 is provided to couple noninverting input (+) to either VREF or VOUT based on an external logic signal. The signal processor in FIG. 3 operates in unipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to VOUT and operates in bipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to VREF. Otherwise the signal processor in FIG. 3 operates in essentially the same manner as those described above in FIGS. 1 and 2 based on the selected mode. The additional external op-amp 52 (and switch 56) adds an offset and, as such, may provide less than optimum dc performance of the signal processor.
Additionally, the ac performance of the signal processor is not optimum due to the finite bandwidth and slew rate of this op amp. A specific implementation of the circuit shown in FIG. 3 is shown in the data sheet for LTC 1597 produced by Linear Technology Corporation of Milpitas, Calif.
Accordingly, it is the object of this invention to provide methods and apparatus for varying the circuit configuration, output voltage range and level of a signal processor in a monolithic solution without the need to add substantial external circuitry, complexity and cost.
The signal processor of the present invention includes a converter circuit and utilizes resistors (or other suitable impedance elements) and programmable switches to control whether the signal processor operates in unipolar or bipolar mode, to set the output voltage range, the level of the circuit and/or to provide an asymmetrical range for output signal. Sets of resistors and programmable switches are preferably provided in a level resistor circuit and/or a feedback resistor circuit to enable the invention.
In an alternative embodiment a signal processor that receives an input signal, a first control word and a second control word, and provides an output signal is provided. The signal processor includes at least two control elements, each of which receives an input signal and a control word and provides a respective intermediate signal. The input signal for one of the control elements is the output signal of the signal processor. This embodiment of the signal processor also includes a summing element that receives a combination of the intermediate signals such that the level, linearity or output signal range of the output signal are programmable based on the control words.
In one embodiment, the signal processor can include a programmable level circuit which functions as a third control element, receives an additional digital word, and preferably serves to adjust the level of the circuit.
Additionally, the present invention can preferably use a single reference voltage to provide an asymmetrical output range by selecting the appropriate resistor and switch combination for the level and feedback resistor circuits.
The present invention also provides for a method of varying the configuration, output voltage range or level of a signal processor. The method determines the mode of operation of the circuit (e.g., unipolar or bipolar), the output voltage range or the level of output signal using programmable switches.
Another embodiment of the invention is a signal processor circuit that receives an input signal and produces an output signal based on the input signal.
The signal processor circuit preferably includes at least one processing element that is adapted to perform a process on the input signal in order to produce the output signal. The signal processor circuit preferably provides a signal-dependent current.
The signal processor circuit preferably also includes a signal level node and a buffer coupled between the processing element and the signal level node. The buffer buffers the signal level node from the signal dependent current.